Generally, metal-oxide semiconductor transistors include a substrate made of a semiconductor material such as silicon. The transistors typically include a source region, a channel region and a drain region within the substrate. The channel region is located between the source and the drain regions. A gate stack, which usually includes a conductive material, a gate oxide layer and sidewall spacers, is generally provided above the channel region. More particularly, the gate oxide layer is typically provided on the substrate over the channel region, while the gate conductor is provided above the gate oxide layer. The sidewall spacers help protect the sidewalls of the gate conductor.
The current flowing through a channel, which has a given electric field across it, is generally directly proportional to the mobility of the carriers in the channel. Thus, by increasing the mobility of the carriers in the channel, the operation speed of the transistor can be increased. Also, mechanical stresses within a semiconductor device substrate can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics.
Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the n-type devices (e.g., NFETs) and/or p-type devices (e.g., PFETs). However, the same stress component, for example tensile stress or compressive stress, improves the device characteristics of one type of device (i.e., n-type device or p-type device) while discriminatively affecting the characteristics of the other type device. By way of example, a tensile stress will improve the performance of an NFET and a compressive force will improve the performance of a PFET. Thus, in order to maximize the performance of both NFETs and PFETs within integrated circuit (IC) devices, the stress components should be engineered and applied differently for NFETs and PFETs.
To selectively create tensile stress in an NFET and compressive stress in a PFET, distinctive processes and different combinations of materials are used. For example, a trench isolation structure has been proposed for forming the appropriate stresses in the NFETs and PFETs, respectively. When this method is used, the isolation region for the NFET device contains a first isolation material which applies a first type of mechanical stress on the NFET device in a longitudinal direction (parallel to the direction of current flow) and in a transverse direction (perpendicular to the direction of current flow). Further, a first isolation region and a second isolation region are provided for the PFET and each of the isolation regions of the PFET device applies a unique mechanical stress on the PFET device in the transverse and longitudinal directions.
Alternatively, methods have been proposed for providing a single strain layer on the entire device, using two lithography masks for patterning. By way of one illustrative example, a single nitride layer with a first stress component is placed over the entire structure, e.g., NFET and PFET, after silicidation. In the example discussed herein, the first nitride layer imposes a tensile component within the channel of the NFET. An oxide hard mask is then deposited over the nitride layer, and a photo resist is placed over one of the transistors, e.g., NFET. A reactive ion etching (RIE) is then performed to remove the hard mask over the PFET and the remaining photo resist over the NFET. A nitride etch is then performed to remove the nitride layer over the PFET.
A nitride layer with a compressive component is then placed over the PFET and the hard mask over the NFET, across a trench isolation structure (STI). This nitride layer will impose a compressive component in the PFET to enhance device performance. A photo resist is then deposited over the nitride layer of the PFET and across the STI. This photo resist also overlaps the tensile nitride layer of the NFET, taking into consideration only the vertical edge of the first nitride layer during the mapping process. A nitrogen etching process is then performed, which etches away the compressive nitrogen layer over portions of the NFET.
However, due to normal alignment errors of the patterning process, e.g., placement of the photoresist and difficulties controlling the etching, an overlap of the nitride layers is formed near the boundary of the compressive nitride layer and the tensile nitride layer. Namely, the compressive nitride layer remains over portions of the hard mask and the tensile nitride layer over a gate poly and the STI, resulting in three layers of material. These overlaps result in subsequent etching difficulties at this overlap region.
These same alignment errors can also cause gaps between the nitride layers; however, such a gap is not very desirable because metal ions such as Cu can diffuse into silicon from back-end-of-the-line process. Thus, it is very important to ensure that there are no gaps. To guarantee that there are no gaps, further compensations are made in the etching process so that the nitride layers fill any gaps. Although such compensation ensures that the nitride layers will prevent such out diffusing, a larger overlap can occur.
In further processing steps, an oxide layer is deposited over the nitride layers, and vias are then etched into the oxide layer. A metal is then placed in the vias to create via contacts to the source and drain regions of the device. However, etching becomes very difficult due to the variations in layer thickness, especially at the overlap of the nitride layers. For example, etching in the overlap region (i.e., over the nitride layers and the hard mask layer) to make contact with the device results in over etching of the remaining portions of the device. On the other hand, etching designed for the portions of the device with one or two layers will result in an under etch of the overlap region. This under etch will result in a layer blocking contact between the device and the contact. (FIG. 1).
While these methods do provide structures that have tensile stresses being applied to the NFET device and compressive stresses being applied to the PFET device, they may require additional materials and/or more complex processing, and thus, resulting in higher cost. Further, due to the inaccuracies of the etching processes, an under etch or over etch can result in portions of the device. In the case of under etching in the overlap region, the contact will be blocked from contacting the device.